FPGA — Intern (Fall 2024)
Astranis
Astranis is on a mission to bridge the digital divide by connecting the four billion people worldwide who currently lack internet access. We're doing this by building the next generation of smaller, more cost-effective spacecraft to bring the world online.
As a team, we’ve launched two satellites into orbit, signed ten commercial deals worth over $1 billion in revenue, raised over $500 million from top global investors, and recruited a team of over 300 world-class engineers. We all work out of our (legendary) San Francisco office, which was once used to build ships during the World Wars.
Our satellites, which operate from geostationary orbit (GEO), weigh only 400 kg and utilize a proprietary software-defined radio payload. Each satellite can connect over two million people, and we’re very excited for the impact we’ll soon have in the Philippines, Peru, Mexico, and more!
Backed by substantial funding and a passionate, collaborative team, we offer a rewarding work environment where you'll learn and make a significant impact, no matter where you are in your career.
Apply and join us on our journey towards global connectivity!
Role:
- RTL Development for FPGA targeted applications
- Work with multiple FPGAs and toolchains
- Interface FPGAs with a variety of peripherals including high speed data converters, memories, MCUs
- Write software to interface and test RTL in hardware
- Collaborate closely with electrical and software engineers
Requirements:
- US Citizenship or Green Card (This is a legal requirement; no exceptions)
- Currently pursuing a B.S. or M.S. in electrical engineering, computer science, computer engineering, or equivalent
- A passion for hardware development, including working in a fast-paced environment and hands-on design and development
- Experience in designing, implementing, and testing high throughput systems implemented on FPGAs
- Proficiency with Verilog/SystemVerilog for synthesis
- Don't meet them all? Not a problem. Please apply even if you do not meet all these criteria.
Bonus:
- Experience with UVM and advanced SystemVerilog verification
- Experience with Xilinx FPGAs
- Experience with Vivado IDE, TCL
- Familiarity with system level estimates and implications of power, thermal, and real estate
- Experience with high speed data converters (ADCs, DACs, JESD204B)
- Experience with circuit level debugging
- Experience with digital communication theory and implementation, such as LDPC implementations
- Experience with space-based systems
- Experience with modern communication systems (RF, IF/IQ, time/freq domains, modulation)
- Experience in at least 1 domain beyond logic design. This could be DSP/radio design, software, hi-rel design (e.g. fault analysis & recover), etc.