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Senior IC Layout (FinFET) Designer

EverSpin Technologies

EverSpin Technologies

Design
Texas, USA
Posted on Friday, May 24, 2024

IC Layout (FinFET) Designer

About Everspin

Headquartered in Chandler, Arizona, Everspin Technologies (Nasdaq: MRAM) is the worldwide leader in designing, manufacturing, and commercially shipping discrete and embedded Magnetoresistive RAM (MRAM) into markets and applications where data persistence and integrity, low latency, and security are paramount. With over 150 Million MRAM products deployed in data center, cloud storage, energy, industrial, automotive, and transportation markets, Everspin has built the strongest and fastest growing foundation of MRAM users in the world. For more information, visit www.everspin.com.

The Role

Reporting to the VP of Engineering, and based in our Austin, Texas location, the IC Layout Design Engineer will work closely with circuit designers to generate topological layouts of high-performance, cutting-edge memory products.

Specific responsibilities will include:

  • Work closely with circuit designers to complete the physical layout and verification of high-performance analog/mixed-signal CMOS Integrated Circuits using Cadence Virtuoso XL Layout and PVS Verification tools in FinFET technologies.
  • Use problem solving skills, experience, and creativity to layout circuits that meet size, schedule, and performance specifications while meeting FinFET technology rules. .
  • Run physical design verification tools to debug, improve, and verify layout blocks.
  • Collaborate with fellow team members on continuous improvement opportunities in the flow, layout techniques, and design methodologies.

Qualifications & competencies

  • Associates or higher degree in Electronic/IC layout CAD specialization or related program.
  • 5+ years’ experience in IC layout design in FinFET technology node.
  • Strong understanding of layout fundamentals and best practices.
  • Solid understanding of semiconductor manufacturing process and DFM techniques.
  • Must be knowledgeable with CAD tools like Cadence Virtuoso XL, PVS/Calibre.
  • Proficient at debugging/fixing LVS/DRC errors.
  • Experience with synthesis/advanced place & route tools (Innovus) is a plus.
  • Must be familiar with Cadence Design Environment (CDE) and Unix OS.
  • Programming knowledge in SKILL is a plus.
  • Must have strong communication skills and be a team player.
  • Unquestionable ethics – treats people with respect; keeps commitments; inspires the trust of others; works with integrity.
  • Commitment to our core values of Leadership, Innovation, Communication, Persistence, Enthusiasm, and Respect.

Physical Demands and Work Environment

  • Occasionally required to stand.
  • Occasionally required to walk.
  • Continually required to sit.
  • Continually required to utilize hand and finger dexterity.
  • Continually required to talk or hear.
  • Continually utilize visual acuity to operate equipment, read technical information,
    and/or use a keyboard.
  • Occasionally required to lift/push/carry items less than 25 pounds.

Additional Comments

  • 2 days per week in office (Tuesday & Thursday)